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ubc.h
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1 /* KallistiOS ##version##
2 
3  kernel/arch/dreamcast/include/dc/ubc.h
4  (C)2002 Dan Potter
5 
6 */
7 
8 /** \file dc/ubc.h
9  \brief User-break controller support.
10 
11  This file defines some functionality for using the SH4 UBC.
12 
13  \author Dan Potter
14 */
15 
16 #ifndef __DC_UBC_H
17 #define __DC_UBC_H
18 
19 #include <sys/cdefs.h>
20 __BEGIN_DECLS
21 
22 #include <arch/types.h>
23 
24 /* From the SH-4 PDF */
25 /** \defgroup ubc_regs UBC Registers
26 
27  These registers are as documented in the SH4 manual. Consult it for more
28  information.
29 
30  @{
31 */
32 #define BARA (*((vuint32*)0xFF200000)) /**< \brief BARA register. */
33 #define BASRA (*((vuint8*)0xFF000014)) /**< \brief BASRA register. */
34 #define BAMRA (*((vuint8*)0xFF200004)) /**< \brief BAMRA register. */
35 #define BBRA (*((vuint16*)0xFF200008)) /**< \brief BBRA register. */
36 #define BARB (*((vuint32*)0xFF20000C)) /**< \brief BARB register. */
37 #define BASRB (*((vuint8*)0xFF000018)) /**< \brief BASRB register. */
38 #define BAMRB (*((vuint8*)0xFF200010)) /**< \brief BAMRB register. */
39 #define BBRB (*((vuint16*)0xFF200014)) /**< \brief BBRB register. */
40 #define BRCR (*((vuint16*)0xFF200020)) /**< \brief BRCR register. */
41 /** @} */
42 
43 /* These are inlined to avoid complications with using them */
44 
45 /** \brief Pause after setting UBC parameters. */
46 static inline void ubc_pause() {
47  __asm__ __volatile__("nop\n"
48  "nop\n"
49  "nop\n"
50  "nop\n"
51  "nop\n"
52  "nop\n"
53  "nop\n"
54  "nop\n"
55  "nop\n"
56  "nop\n"
57  "nop\n");
58 }
59 
60 /** \brief Disable all UBC breakpoints. */
61 static inline void ubc_disable_all() {
62  BBRA = 0;
63  BBRB = 0;
64  ubc_pause();
65 }
66 
67 /** \brief Set a UBC data-write breakpoint at the given address.
68  \param address The address to set the breakpoint at
69 */
70 static inline void ubc_break_data_write(uint32 address) {
71  BASRA = 0; /* ASID = 0 */
72  BARA = address; /* Break address */
73  BAMRA = 4; /* Mask the ASID */
74  BRCR = 0; /* Nothing special, clear all flags */
75  BBRA = 0x28; /* Operand write cycle, no size constraint */
76  ubc_pause();
77 }
78 
79 /** \brief Set a UBC instruction access breakpoint at the given address.
80  \param address The address to set the breakpoint at.
81  \param use_dbr Use the DBR register as the base for the exception.
82 */
83 static inline void ubc_break_inst(uint32 address, int use_dbr) {
84  BASRA = 0; /* ASID = 0 */
85  BARA = address; /* Break address */
86  BAMRA = 4; /* Mask the ASID */
87 
88  if(use_dbr) {
89  BRCR = 1; /* Use the DBR as the base for the IRQ */
90  }
91  else {
92  BRCR = 0;
93  }
94 
95  BBRA = 0x1C; /* Instruction cycle, no size constraint */
96  ubc_pause();
97 }
98 
99 /* More to come.... */
100 
101 __END_DECLS
102 
103 #endif /* __DC_UBC_H */
104 
Common integer types.
static void ubc_disable_all()
Disable all UBC breakpoints.
Definition: ubc.h:61
#define BBRB
BBRB register.
Definition: ubc.h:39
#define BBRA
BBRA register.
Definition: ubc.h:35
static void ubc_pause()
Pause after setting UBC parameters.
Definition: ubc.h:46
static void ubc_break_inst(uint32 address, int use_dbr)
Set a UBC instruction access breakpoint at the given address.
Definition: ubc.h:83
unsigned long uint32
32-bit unsigned integer
Definition: types.h:28
#define BAMRA
BAMRA register.
Definition: ubc.h:34
static void ubc_break_data_write(uint32 address)
Set a UBC data-write breakpoint at the given address.
Definition: ubc.h:70
#define BARA
BARA register.
Definition: ubc.h:32
#define BRCR
BRCR register.
Definition: ubc.h:40
#define BASRA
BASRA register.
Definition: ubc.h:33