KallistiOS
##version##
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Macros | |
#define | RT_IDR0 0x00 |
MAC address. More... | |
#define | RT_MAR0 0x08 |
Multicast filter. More... | |
#define | RT_TXSTATUS0 0x10 |
Transmit status (4 32bit regs) More... | |
#define | RT_TXADDR0 0x20 |
Tx descriptors (also 4 32bit) More... | |
#define | RT_RXBUF 0x30 |
Receive buffer start address. More... | |
#define | RT_RXEARLYCNT 0x34 |
Early Rx byte count. More... | |
#define | RT_RXEARLYSTATUS 0x36 |
Early Rx status. More... | |
#define | RT_CHIPCMD 0x37 |
Command register. More... | |
#define | RT_RXBUFTAIL 0x38 |
Current address of packet read (queue tail) More... | |
#define | RT_RXBUFHEAD 0x3A |
Current buffer address (queue head) More... | |
#define | RT_INTRMASK 0x3C |
Interrupt mask. More... | |
#define | RT_INTRSTATUS 0x3E |
Interrupt status. More... | |
#define | RT_TXCONFIG 0x40 |
Tx config. More... | |
#define | RT_RXCONFIG 0x44 |
Rx config. More... | |
#define | RT_TIMER 0x48 |
A general purpose counter. More... | |
#define | RT_RXMISSED 0x4C |
24 bits valid, write clears More... | |
#define | RT_CFG9346 0x50 |
93C46 command register More... | |
#define | RT_CONFIG0 0x51 |
Configuration reg 0. More... | |
#define | RT_CONFIG1 0x52 |
Configuration reg 1. More... | |
#define | RT_TIMERINT 0x54 |
Timer interrupt register (32 bits) More... | |
#define | RT_MEDIASTATUS 0x58 |
Media status register. More... | |
#define | RT_CONFIG3 0x59 |
Config register 3. More... | |
#define | RT_CONFIG4 0x5A |
Config register 4. More... | |
#define | RT_MULTIINTR 0x5C |
Multiple interrupt select. More... | |
#define | RT_MII_TSAD 0x60 |
Transmit status of all descriptors (16 bits) More... | |
#define | RT_MII_BMCR 0x62 |
Basic Mode Control Register (16 bits) More... | |
#define | RT_MII_BMSR 0x64 |
Basic Mode Status Register (16 bits) More... | |
#define | RT_AS_ADVERT 0x66 |
Auto-negotiation advertisement reg (16 bits) More... | |
#define | RT_AS_LPAR 0x68 |
Auto-negotiation link partner reg (16 bits) More... | |
#define | RT_AS_EXPANSION 0x6A |
Auto-negotiation expansion reg (16 bits) More... | |
#define RT_AS_ADVERT 0x66 |
Auto-negotiation advertisement reg (16 bits)
#define RT_AS_EXPANSION 0x6A |
Auto-negotiation expansion reg (16 bits)
#define RT_AS_LPAR 0x68 |
Auto-negotiation link partner reg (16 bits)
#define RT_CFG9346 0x50 |
93C46 command register
#define RT_CHIPCMD 0x37 |
Command register.
#define RT_CONFIG0 0x51 |
Configuration reg 0.
#define RT_CONFIG1 0x52 |
Configuration reg 1.
#define RT_CONFIG3 0x59 |
Config register 3.
#define RT_CONFIG4 0x5A |
Config register 4.
#define RT_IDR0 0x00 |
MAC address.
#define RT_INTRMASK 0x3C |
Interrupt mask.
#define RT_INTRSTATUS 0x3E |
Interrupt status.
#define RT_MAR0 0x08 |
Multicast filter.
#define RT_MEDIASTATUS 0x58 |
Media status register.
#define RT_MII_BMCR 0x62 |
Basic Mode Control Register (16 bits)
#define RT_MII_BMSR 0x64 |
Basic Mode Status Register (16 bits)
#define RT_MII_TSAD 0x60 |
Transmit status of all descriptors (16 bits)
#define RT_MULTIINTR 0x5C |
Multiple interrupt select.
#define RT_RXBUF 0x30 |
Receive buffer start address.
#define RT_RXBUFHEAD 0x3A |
Current buffer address (queue head)
#define RT_RXBUFTAIL 0x38 |
Current address of packet read (queue tail)
#define RT_RXCONFIG 0x44 |
Rx config.
#define RT_RXEARLYCNT 0x34 |
Early Rx byte count.
#define RT_RXEARLYSTATUS 0x36 |
Early Rx status.
#define RT_RXMISSED 0x4C |
24 bits valid, write clears
#define RT_TIMER 0x48 |
A general purpose counter.
#define RT_TIMERINT 0x54 |
Timer interrupt register (32 bits)
#define RT_TXADDR0 0x20 |
Tx descriptors (also 4 32bit)
#define RT_TXCONFIG 0x40 |
Tx config.
#define RT_TXSTATUS0 0x10 |
Transmit status (4 32bit regs)