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KallistiOS
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KallistiOS
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Macros | |
| #define | EXC_NMI 0x01c0 |
| Nonmaskable interrupt. More... | |
| #define | EXC_IRQ0 0x0200 |
| External IRQ request (level 0) More... | |
| #define | EXC_IRQ1 0x0220 |
| External IRQ request (level 1) More... | |
| #define | EXC_IRQ2 0x0240 |
| External IRQ request (level 2) More... | |
| #define | EXC_IRQ3 0x0260 |
| External IRQ request (level 3) More... | |
| #define | EXC_IRQ4 0x0280 |
| External IRQ request (level 4) More... | |
| #define | EXC_IRQ5 0x02a0 |
| External IRQ request (level 5) More... | |
| #define | EXC_IRQ6 0x02c0 |
| External IRQ request (level 6) More... | |
| #define | EXC_IRQ7 0x02e0 |
| External IRQ request (level 7) More... | |
| #define | EXC_IRQ8 0x0300 |
| External IRQ request (level 8) More... | |
| #define | EXC_IRQ9 0x0320 |
| External IRQ request (level 9) More... | |
| #define | EXC_IRQA 0x0340 |
| External IRQ request (level 10) More... | |
| #define | EXC_IRQB 0x0360 |
| External IRQ request (level 11) More... | |
| #define | EXC_IRQC 0x0380 |
| External IRQ request (level 12) More... | |
| #define | EXC_IRQD 0x03a0 |
| External IRQ request (level 13) More... | |
| #define | EXC_IRQE 0x03c0 |
| External IRQ request (level 14) More... | |
| #define | EXC_TMU0_TUNI0 0x0400 |
| TMU0 underflow. More... | |
| #define | EXC_TMU1_TUNI1 0x0420 |
| TMU1 underflow. More... | |
| #define | EXC_TMU2_TUNI2 0x0440 |
| TMU2 underflow. More... | |
| #define | EXC_TMU2_TICPI2 0x0460 |
| TMU2 input capture. More... | |
| #define | EXC_RTC_ATI 0x0480 |
| RTC alarm interrupt. More... | |
| #define | EXC_RTC_PRI 0x04a0 |
| RTC periodic interrupt. More... | |
| #define | EXC_RTC_CUI 0x04c0 |
| RTC carry interrupt. More... | |
| #define | EXC_SCI_ERI 0x04e0 |
| SCI Error receive. More... | |
| #define | EXC_SCI_RXI 0x0500 |
| SCI Receive ready. More... | |
| #define | EXC_SCI_TXI 0x0520 |
| SCI Transmit ready. More... | |
| #define | EXC_SCI_TEI 0x0540 |
| SCI Transmit error. More... | |
| #define | EXC_WDT_ITI 0x0560 |
| Watchdog timer. More... | |
| #define | EXC_REF_RCMI 0x0580 |
| Memory refresh compare-match interrupt. More... | |
| #define | EXC_REF_ROVI 0x05a0 |
| Memory refresh counter overflow interrupt. More... | |
| #define | EXC_UDI 0x0600 |
| Hitachi UDI. More... | |
| #define | EXC_GPIO_GPIOI 0x0620 |
| I/O port interrupt. More... | |
| #define | EXC_DMAC_DMTE0 0x0640 |
| DMAC transfer end (channel 0) More... | |
| #define | EXC_DMAC_DMTE1 0x0660 |
| DMAC transfer end (channel 1) More... | |
| #define | EXC_DMAC_DMTE2 0x0680 |
| DMAC transfer end (channel 2) More... | |
| #define | EXC_DMAC_DMTE3 0x06a0 |
| DMAC transfer end (channel 3) More... | |
| #define | EXC_DMA_DMAE 0x06c0 |
| DMAC address error. More... | |
| #define | EXC_SCIF_ERI 0x0700 |
| SCIF Error receive. More... | |
| #define | EXC_SCIF_RXI 0x0720 |
| SCIF Receive ready. More... | |
| #define | EXC_SCIF_BRI 0x0740 |
| SCIF break. More... | |
| #define | EXC_SCIF_TXI 0x0760 |
| SCIF Transmit ready. More... | |
These exceptions are caused by interrupt requests. These generally are from peripheral devices, but NMIs, timer interrupts, and DMAC interrupts are also included here.
| #define EXC_DMA_DMAE 0x06c0 |
DMAC address error.
| #define EXC_DMAC_DMTE0 0x0640 |
DMAC transfer end (channel 0)
| #define EXC_DMAC_DMTE1 0x0660 |
DMAC transfer end (channel 1)
| #define EXC_DMAC_DMTE2 0x0680 |
DMAC transfer end (channel 2)
| #define EXC_DMAC_DMTE3 0x06a0 |
DMAC transfer end (channel 3)
| #define EXC_GPIO_GPIOI 0x0620 |
I/O port interrupt.
| #define EXC_IRQ0 0x0200 |
External IRQ request (level 0)
| #define EXC_IRQ1 0x0220 |
External IRQ request (level 1)
| #define EXC_IRQ2 0x0240 |
External IRQ request (level 2)
| #define EXC_IRQ3 0x0260 |
External IRQ request (level 3)
| #define EXC_IRQ4 0x0280 |
External IRQ request (level 4)
| #define EXC_IRQ5 0x02a0 |
External IRQ request (level 5)
| #define EXC_IRQ6 0x02c0 |
External IRQ request (level 6)
| #define EXC_IRQ7 0x02e0 |
External IRQ request (level 7)
| #define EXC_IRQ8 0x0300 |
External IRQ request (level 8)
| #define EXC_IRQ9 0x0320 |
External IRQ request (level 9)
| #define EXC_IRQA 0x0340 |
External IRQ request (level 10)
| #define EXC_IRQB 0x0360 |
External IRQ request (level 11)
| #define EXC_IRQC 0x0380 |
External IRQ request (level 12)
| #define EXC_IRQD 0x03a0 |
External IRQ request (level 13)
| #define EXC_IRQE 0x03c0 |
External IRQ request (level 14)
| #define EXC_NMI 0x01c0 |
Nonmaskable interrupt.
| #define EXC_REF_RCMI 0x0580 |
Memory refresh compare-match interrupt.
| #define EXC_REF_ROVI 0x05a0 |
Memory refresh counter overflow interrupt.
| #define EXC_RTC_ATI 0x0480 |
RTC alarm interrupt.
| #define EXC_RTC_CUI 0x04c0 |
RTC carry interrupt.
| #define EXC_RTC_PRI 0x04a0 |
RTC periodic interrupt.
| #define EXC_SCI_ERI 0x04e0 |
SCI Error receive.
| #define EXC_SCI_RXI 0x0500 |
SCI Receive ready.
| #define EXC_SCI_TEI 0x0540 |
SCI Transmit error.
| #define EXC_SCI_TXI 0x0520 |
SCI Transmit ready.
| #define EXC_SCIF_BRI 0x0740 |
SCIF break.
| #define EXC_SCIF_ERI 0x0700 |
SCIF Error receive.
| #define EXC_SCIF_RXI 0x0720 |
SCIF Receive ready.
| #define EXC_SCIF_TXI 0x0760 |
SCIF Transmit ready.
| #define EXC_TMU0_TUNI0 0x0400 |
TMU0 underflow.
| #define EXC_TMU1_TUNI1 0x0420 |
TMU1 underflow.
| #define EXC_TMU2_TICPI2 0x0460 |
TMU2 input capture.
| #define EXC_TMU2_TUNI2 0x0440 |
TMU2 underflow.
| #define EXC_UDI 0x0600 |
Hitachi UDI.
| #define EXC_WDT_ITI 0x0560 |
Watchdog timer.
1.8.7
