MMU TLB entry for a single page. More...

#include <arch/mmu.h>

Data Fields
uint32	physical: 18
	Physical page ID – 18 bits. More...

uint32	prkey: 2
	Protection key data – 2 bits. More...

uint32	valid: 1
	Valid mapping – 1 bit. More...

uint32	shared: 1
	Shared between procs – 1 bit. More...

uint32	cache: 1
	Cacheable – 1 bit. More...

uint32	dirty: 1
	Dirty – 1 bit. More...

uint32	wthru: 1
	Write-thru enable – 1 bit. More...

uint32	blank: 7
	Reserved – 7 bits. More...

uint32	pteh
	Pre-built PTEH value. More...

uint32	ptel
	Pre-built PTEL value. More...

Detailed Description

MMU TLB entry for a single page.

The TLB entries on the SH4 are a single 32-bit dword in length. We store some other data here too for ease of use.

Field Documentation

uint32 mmupage::blank

Reserved – 7 bits.

uint32 mmupage::cache

Cacheable – 1 bit.

uint32 mmupage::dirty

Dirty – 1 bit.

uint32 mmupage::physical

Physical page ID – 18 bits.

uint32 mmupage::prkey

Protection key data – 2 bits.

uint32 mmupage::pteh

Pre-built PTEH value.

uint32 mmupage::ptel

Pre-built PTEL value.

uint32 mmupage::shared

Shared between procs – 1 bit.

uint32 mmupage::valid

Valid mapping – 1 bit.

uint32 mmupage::wthru

Write-thru enable – 1 bit.

The documentation for this struct was generated from the following file: