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asic.h File Reference

Dreamcast ASIC event handling support. More...

#include <sys/cdefs.h>
#include <arch/types.h>

Go to the source code of this file.

Macros

#define ASIC_EVT_PVR_RENDERDONE   0x0002
 Render completed.
#define ASIC_EVT_PVR_SCANINT1   0x0003
 Scanline interrupt 1.
#define ASIC_EVT_PVR_SCANINT2   0x0004
 Scanline interrupt 2.
#define ASIC_EVT_PVR_VBLINT   0x0005
 VBL interrupt.
#define ASIC_EVT_PVR_OPAQUEDONE   0x0007
 Opaque list completed.
#define ASIC_EVT_PVR_OPAQUEMODDONE   0x0008
 Opaque modifiers completed.
#define ASIC_EVT_PVR_TRANSDONE   0x0009
 Transparent list completed.
#define ASIC_EVT_PVR_TRANSMODDONE   0x000a
 Transparent modifiers completed.
#define ASIC_EVT_PVR_DMA   0x0013
 PVR DMA complete.
#define ASIC_EVT_PVR_PTDONE   0x0015
 Punch-thrus completed.
#define ASIC_EVT_PVR_PRIMOUTOFMEM   0x0202
 Out of primitive memory.
#define ASIC_EVT_PVR_MATOUTOFMEM   0x0203
 Out of matrix memory.
#define ASIC_EVT_GD_COMMAND   0x0100
 GD-Rom Command Status.
#define ASIC_EVT_GD_DMA   0x000e
 GD-Rom DMA complete.
#define ASIC_EVT_GD_DMA_OVERRUN   0x020d
 GD-Rom DMA overrun.
#define ASIC_EVT_GD_DMA_ILLADDR   0x020c
 GD-Rom DMA illegal address.
#define ASIC_EVT_MAPLE_DMA   0x000c
 Maple DMA complete.
#define ASIC_EVT_MAPLE_ERROR   0x000d
 Maple error (?)
#define ASIC_EVT_SPU_DMA   0x000f
 SPU (G2 channel 0) DMA complete.
#define ASIC_EVT_SPU_IRQ   0x0101
 SPU interrupt.
#define ASIC_EVT_G2_DMA0   0x000f
 G2 DMA channel 0 complete.
#define ASIC_EVT_G2_DMA1   0x0010
 G2 DMA channel 1 complete.
#define ASIC_EVT_G2_DMA2   0x0011
 G2 DMA channel 2 complete.
#define ASIC_EVT_G2_DMA3   0x0012
 G2 DMA channel 3 complete.
#define ASIC_EVT_EXP_8BIT   0x0102
 Modem / Lan Adapter.
#define ASIC_EVT_EXP_PCI   0x0103
 BBA IRQ.
#define ASIC_IRQD_A   (*(vuint32*)0xa05f6910)
 IRQD first register.
#define ASIC_IRQD_B   (*(vuint32*)0xa05f6914)
 IRQD second register.
#define ASIC_IRQD_C   (*(vuint32*)0xa05f6918)
 IRQD third register.
#define ASIC_IRQB_A   (*(vuint32*)0xa05f6920)
 IRQB first register.
#define ASIC_IRQB_B   (*(vuint32*)0xa05f6924)
 IRQB second register.
#define ASIC_IRQB_C   (*(vuint32*)0xa05f6928)
 IRQB third register.
#define ASIC_IRQ9_A   (*(vuint32*)0xa05f6930)
 IRQ9 first register.
#define ASIC_IRQ9_B   (*(vuint32*)0xa05f6934)
 IRQ9 second register.
#define ASIC_IRQ9_C   (*(vuint32*)0xa05f6938)
 IRQ9 third register.
#define ASIC_ACK_A   (*(vuint32*)0xa05f6900)
 IRQD ACK register.
#define ASIC_ACK_B   (*(vuint32*)0xa05f6904)
 IRQB ACK register.
#define ASIC_ACK_C   (*(vuint32*)0xa05f6908)
 IRQ9 ACK register.
#define ASIC_IRQ9   1
 IRQ level 9.
#define ASIC_IRQB   2
 IRQ level B (11)
#define ASIC_IRQD   3
 IRQ level D (13)
#define ASIC_IRQ_DEFAULT   0
 Pick an IRQ level for me!

Typedefs

typedef void(* asic_evt_handler )(uint32 code)
 ASIC event handler type.

Functions

int asic_evt_set_handler (uint32 code, asic_evt_handler handler)
 Set or remove an ASIC handler.
void asic_evt_disable_all ()
 Disable all ASIC events.
void asic_evt_disable (uint32 code, int irqlevel)
 Disable one ASIC event.
void asic_evt_enable (uint32 code, int irqlevel)
 Enable an ASIC event.
void asic_init ()
 Init ASIC events.
void asic_shutdown ()
 Shutdown ASIC events, disabling all hooks.

Detailed Description

Dreamcast ASIC event handling support.

This file provides definitions of the events that the ASIC (a part of the PVR) in the Dreamcast can trigger as IRQs, and ways to set responders for those events. Pretty much, this covers all IRQs that aren't generated internally in the SH4 (SCIF and the SH4 DMAC can generate their own IRQs, as well as the trapa instruction, and various exceptions – those are not dealt with here).

Author:
Dan Potter